Resistance of a gate electrode may be an important factor in determining an operational speed of a semiconductor device. To reduce resistance of a poly gate electrode, for example, a silicide layer may be formed on the poly gate electrode.
FIGS. 1A to 1G are example sectional diagrams illustrating a method of fabricating a related art semiconductor device.
Referring to FIG. 1A, a gate electrode material such as polysilicon may be formed on silicon substrate 100, and gate electrode material may be etched using a photoresist pattern as a mask. The photoresist pattern may be removed and a cleaning process may be performed thereon to form gate electrode 110.
Referring to FIG. 1B, poly oxide layer 120 may be formed on a surface, for example the entire upper surface, of silicon substrate 100 including gate electrode 110. Poly oxide layer 120 may recover or correct damage caused by plasma generated during the etching process and may prevent damage that may be caused during an implant process that may be performed later. Such an implant process may be an ion implant process to form an N lightly doped drain (LDD).
Referring to FIG. 1C, cap oxide layer 130 may be formed on poly oxide layer 120. Cap oxide layer 130 may serve as an etch stop layer, and may prevent damage caused by an implant process to be performed after the ion implant process for forming an N LDD. Such an implant process may include an ion implant process for forming a P LDD. Cap oxide layer 130 may also prevent damage caused during an etching process of a sidewall nitride. Cap oxide layer 130 may be formed using a tetra ethyl ortho silicate (TEOS).
Referring to FIG. 1D, nitride layer 140 may be formed on a surface (for example, an entire upper surface) of cap oxide layer 130. Nitride layer 140 may be used to form sidewalls and may be formed using a deposition process.
Referring to FIG. 1E, nitride layer 140 may be etched to form sidewalls 141 and 142 at both sides of gate electrode 110. A source/drain implant process may then be performed.
Referring to FIG. 1F, poly oxide layer 120 and cap oxide layer 130 on silicon substrate 100 and gate electrode 110 may be removed, for example using dry and wet etching processes. This may be done before forming a silicide layer having lower specific resistance than specific resistance of a poly gate on a surface of silicon substrate 100 and a surface of gate electrode 110 in order to reduce resistance of a poly gate.
Referring to FIG. 1G, silicide layer 150 may be formed on an exposed surface of substrate 100 and an exposed surface of the gate electrode. Silicide layer 150 may be formed by depositing a metal layer such as a Co layer, a Ti layer, and/or a Ni layer on a surface of the structure illustrated in FIG. 1F, for example using a sputtering process and then performing a patterning process, a stripping process, a heat treatment process, and the like.
According to the above-mentioned method of related art, as a silicide layer having lower specific resistance than specific resistance of a poly gate may be formed on an exposed surface of a substrate and a gate, resistance of a poly gate may be reduced. However, since the silicide layer may be formed on only the upper surface of the gate, there may be a limitation in reducing resistance.